1. Technical Field
The present invention relates to a digital phase locked loop (DPLL) clock recovery scheme and, more particularly, to a DPLL clock recovery scheme useful with fast acquisition/burst mode applications.
2. Description of the Prior Art
For various types of digital communication systems, it is necessary for the receiver of the information to become synchronized with the transmitted data in order to insure the validity of the received data. In most cases, the receiver includes circuits, known as clock recovery circuits, to perform this task. Many different clock recovery schemes have been developed in the past for long haul and data link applications. Most of these clock recovery schemes utilize an analog PLL arrangement, which typically comprises a phase detector (to compare the phase of the received digital data signal with that of a clock signal), a low pass filter to convert an error signal from the phase detector to an error voltage, and a voltage-controlled oscillator (VCO) having an output frequency that is controlled by the generated error voltage. Most analog PLL circuits, however, are relatively complex and contain various capacitors and resistor components which cannot be easily integrated to form a monolithic structure.
Digital phase-locked loop recovery schemes have also been utilized in the past. One such arrangement being disclosed in U.S. Pat. No. 3,983,498 issued to C. J. Malek on Sept. 28, 1976. Malek utilizes an oscillator, programmable frequency divider, phase detector, and data transition detector. The transition detector is used to generate a pulse of defined width at each data transition. The oscillator is used to generate a fixed frequency signal which is subsequently divided down to the desired clock frequency by the programmable frequency divider. To synchronize the phase of the clock signal with the data transitions, the phase of the data is compared with the phase of the oscillator in the phase detector. Depending upon whether the clock phase leads or lags the data phase, the divisor of the programmable divider is adjusted so as to advance or retard the clock phase to achieve synchronization. A problem with the Malek DPLL scheme, however, is that the adjustments to the clock phase are made at every data transition, tending to cause excessive phase jitter in the clock output cycle. An alternative DPLL arrangement which addresses this problem is disclosed in U.S. Pat. No. 4,280,099 issued to G. D. Rattlingourd on July 21, 1981. In the Rattlingourd arrangement, the clock reference signal is phase matched with the digital data by comparing the positive going and negative edges of the data with the clocking edge of the clock signal. A hard decision is made on the relative phase of the clock signal and the data only after several edge transitions have occurred. By waiting through a number of edge transitions, the amount of jitter in the recovered clock signal will be greatly reduced. However, there are many applications which require the fast acquisition of the recovered clock, broadcast Local Area Networks (LANs) and various burst mode communication systems, being only two examples. The relatively long acquisition time of the Rattlingourd arrangement would be unacceptable for these applications.
An alternative high speed DPLL clock recovery scheme is disclosed in U.S. Pat. No. 4,584,695 issued to H. Wong et al. on Apr. 22, 1986. The Wong et al. arrangement utilizes a multi-phase driver clock to generate a series of output clock signals which are phase-offset from one another. One of the output clock signals is used to sample the incoming Manchester encoded data at locations before, nominally at, and after a predicted clock edge. The sampled bit pattern then indicates whether a leading or lagging phase clock signal should be substituted for the present clock signal. Although the Wong et al. arrangement may be considered an advance over other prior art techniques, it is limited to situations employing Manchester encoded data. That is, the Wong et al. recovery scheme requires the sampling of a received data pattern containing a mid-bit transition, and produces as the output a decoded representation of the Manchester data.
Therefore, a need remains in the prior art for a clock recovery scheme which can provide fast acquisition of the clock, regardless of the type of encoding of the incoming data stream.